Principal Engineer – SoC Physical Verification

About the role

We are looking for an experienced Principal Engineer to lead physical verification sign‑off for next‑generation logic, memory‑centric SoCs and advanced‑node designs. The role ensures tape‑out ready silicon by driving DRC, LVS, ERC, PERC, DFM and reliability checks while collaborating with physical design, CAD, RTL, product engineering, EDA vendors and foundry teams.

Key responsibilities

• Own full‑chip and hierarchical/block physical verification sign‑off, including DRC, LVS, ERC, PERC, antenna, DFM, density, metal fill, CMP and reliability checks.
• Debug, customize and deploy foundry‑qualified rule decks, manage waivers and ensure clean closure for advanced‑node designs.
• Perform reliability verification such as ESD, latch‑up, electromigration, floating nets, multi‑power domain and connectivity checks.
• Support parasitic RC extraction and correlate verification results with implementation and silicon measurements.
• Develop and maintain automation, regression infrastructure, scripting frameworks and AI‑assisted workflows.
• Collaborate closely with PD, CAD, RTL, product engineering, EDA vendors and foundries (including direct TSMC interaction) from project kick‑off through tape‑out.

Required profile

• Experience in full‑chip or block‑level physical verification for advanced‑node SoCs, memory or heterogeneous integration designs.
• Strong expertise in DRC, LVS, ERC, PERC, DFM, antenna and reliability verification methodologies.
• Hands‑on work with advanced technology nodes (22nm, 16nm, 7nm, 5nm and below).
• Good understanding of RTL‑to‑GDSII flows, extraction methodologies and physical design impacts.
• MS/PhD in Electrical Engineering, Computer Engineering or related field.

Required skills

• Physical verification tools: Mentor Calibre, Synopsys IC Validator, Cadence Pegasus.
• Implementation & extraction tools: Synopsys ICC2/Fusion Compiler, Cadence Innovus, Synopsys StarRC, Cadence Quantus.
• Scripting/automation: Python, Tcl, Perl, AI/ML‑enabled verification frameworks.
• Methodologies: DRC, LVS, ERC, PERC, DFM, antenna, reliability verification, post‑silicon debug and yield analysis.