EMIR / Power Integrity Engineer

About the role

We are looking for a skilled EMIR / Power Integrity Engineer to join our SoC Physical Design team. The role focuses on power delivery network planning, power integrity analysis, EMIR verification, and sign‑off for advanced semiconductor designs.

Key responsibilities

• Perform Power Integrity and EMIR analysis for complex SoC, subsystem, and IP designs.
• Develop, analyze, and optimize Power Delivery Networks (PDN) to meet performance, power, and reliability requirements.
• Execute static and dynamic IR drop, and electromigration analysis throughout the design cycle.
• Define simulation methodologies, run setups, and sign‑off criteria for power integrity verification.
• Identify, debug, and resolve EM, static IR, and dynamic IR violations, providing ECO solutions such as grid enhancements, strap optimization, decap insertion, and layout modifications.
• Collaborate with Physical Design, CAD, RTL, Package, and Reliability teams and automate flows using scripting languages.

Required profile

• Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.
• 5+ years of ASIC/SoC EMIR experience.
• Strong analytical, debugging, and communication skills.
• Experience with advanced technology nodes (7nm, 5nm, 3nm or below).

Required skills

• Power Delivery Networks (PDN) design and optimization.
• Electromigration (EM) and static/dynamic IR drop analysis.
• UPF and low‑power design methodologies.
• Cadence Voltus, Ansys RedHawk/RedHawk‑SC, Synopsys PrimeRail/PrimePower.
• Cadence Innovus, Synopsys ICC2, FC_SHELL for power grid implementation.
• Scripting in Tcl, Python, Perl, Shell.