Principal Engineer – SoC Physical Design

About the role

We are looking for a highly motivated Principal Engineer with deep expertise in full‑chip physical design to lead the implementation of complex ASIC/SoC projects from architecture definition through tape‑out.

Key responsibilities

• Partner with Front‑End and Architecture teams to drive physical design considerations early in the development cycle.
• Lead full‑chip implementation activities including floorplanning, power planning, clock distribution, place‑and‑route, timing closure and sign‑off.
• Define project milestones, track progress, manage dependencies and ensure tape‑out schedules are met.
• Collaborate with STA, DFT, RTL, Verification, Power Integrity and Packaging teams to resolve timing, congestion, power, IR‑drop, EM and signal‑integrity issues.
• Mentor engineers and continuously improve design methodologies and automation flows.

Required profile

• 15+ years of ASIC/SoC physical design experience with multiple successful tape‑outs.
• Hands‑on experience with large‑scale SoCs (>20M gates, >1 GHz) and advanced nodes (22nm to 5nm and below).
• Strong leadership skills and ability to drive execution across geographically distributed teams.

Required skills

• Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC, PrimePower.
• Cadence Innovus, Tempus, Voltus, Quantus.
• Physical verification tools: Calibre, IC Validator, Pegasus.
• Power‑integrity and sign‑off tools: RedHawk, Voltus, PrimePower.
• Scripting/automation: TCL, Perl, Python, Shell scripting.