Principal STA / Constraints Sign‑Off Engineer

About the role

We are looking for a highly motivated Principal STA / Constraints Sign‑Off Engineer to lead timing sign‑off and methodology development for advanced‑node SoC and IP designs. The role combines deep technical expertise with hands‑on leadership to ensure successful tape‑outs with best‑in‑class quality, performance, power and area.

Key responsibilities

• Own and drive timing sign‑off methodologies across advanced technology nodes for SoC/IP blocks.
• Develop, review and validate SDC constraints, timing exceptions and multi‑mode multi‑corner (MMMC) environments.
• Lead setup, hold, SI, OCV/AOCV/POCV and timing closure activities through final sign‑off.
• Drive timing correlation across synthesis, implementation, extraction and sign‑off flows and support ECO closure and low‑power timing analysis.

Required profile

• BS/MS in Electrical Engineering or related field with 12+ years of experience in STA, timing sign‑off and ASIC/SoC implementation.
• Strong hands‑on expertise with Synopsys PrimeTime, ICC2/Fusion Compiler, StarRC, ICV and Cadence Tempus, Innovus, Voltus.
• Proven ability to develop automation scripts and methodology documentation.
• Excellent debugging, analytical and technical leadership skills.

Required skills

• PrimeTime (PT/PT‑SI/PT‑PX), SDC development, MMMC analysis, OCV/AOCV/POCV, crosstalk, ECO methodologies.
• Scripting in Tcl, Python and Perl.
• Knowledge of UPF, low‑power design, EMIR, thermal sign‑off flows.
• Familiarity with high‑speed protocols such as PCIe, DDR, UCIE, ABB, PLLs.