Principal Physical Design Engineer – Full Chip Expert

About the role

Aion Silicon is looking for a Principal Physical Design Engineer who will own the end‑to‑end physical implementation of complex SoCs and ASICs. This senior technical leader will guide full‑chip floorplanning, placement, routing and sign‑off across advanced technology nodes while mentoring a global design team.

Key responsibilities

• Lead full‑chip physical implementation for high‑performance SoC and ASIC projects.
• Define chip‑level physical design strategies, methodologies and best practices.
• Coordinate with RTL, STA, DFT, packaging, foundry and EDA partners to achieve design closure.
• Mentor and coach physical design engineers, fostering capability growth.
• Review and approve block‑level deliverables before integration.
• Drive technical reviews, debug sessions and tape‑out closure activities.
• Support recruitment and represent Aion Silicon at universities, conferences and industry events.

Required profile

• 10+ years of physical design experience with a proven record of full‑chip delivery.
• Deep knowledge of advanced nodes (7nm, 5nm and below) and multiple tape‑outs.
• Demonstrated leadership and mentorship abilities.
• Strong stakeholder management and communication skills.

Required skills

• Full‑chip floorplanning and macro placement.
• Power grid design, multi‑voltage domains and power‑gating.
• Clock‑tree synthesis (CTS) and multi‑domain clock architectures.
• Placement, routing, signal‑integrity, crosstalk and antenna mitigation.
• STA sign‑off, MCMM timing analysis and timing ECO.
• Experience with advanced‑node design flows (7nm, 5nm, below).